CISC And RISC: Classification of Instruction Set Architecture

Earlier Article: Instruction Set Architecture: Basic Concepts

An important aspect of computer architecture is the design of the instruction set for the processor. The instruction set chosen for a particular computer determines the way that machine language programs are constructed. These are of basically two types, which are given as follows:

Complex Instruction Set Computer (CISC)

If the control unit contains a number of micro-electronic circuitry to generate a set of control signals and each microcircuitry is activated by a micro-code, this design approach is called CISC design.

CISC processors are mostly used by: Intel 386, 486, Pentium, Pentium Pro, Pentium II, Pentium III processors etc.

CISC chips have a large, variable length and complex instructions and generally make use of complex addressing modes. Different machine programs can be executed on CISC machine. Since CISC processors possess so many processing features, the job of machine language programmers becomes easier. But at the same time, they are complex as well as expensive to produce. Nowadays, most of the personal computers use CISC processors.

Reduced Instruction Set Computer (RISC)

To execute each instruction, if there is separate electronic circuitry in the control unit, which produces all the necessary signals, this approach of the design of the control section of the processor is called RISC design.

It is also called hard-wired approach. Examples of RISC processors: IBM RS6000, MC88100 processors etc. RISC processors use a small and limited number of instructions and mostly use hardwired control unit. These consume less power and are having a relatively higher performance.

RISC processors use simple addressing modes and RISC instruction is of uniform fixed length. Since RISC processors have a small instruction set, they place extra demand on programmers. However, RISC processors are faster, less complex and less expensive than CISC processors because of their simpler design.

Since RISC design uses more lines of code hence, more RAM is needed to store the assembly level instructions. Also, the compiler must also perform more work to convert a high-level language statement into code of this form.

How do these work? RISC and CISC in Action:

Let's consider a simple instruction of multiplication of two numbers in the memory.

Suppose that the main memory is divided into locations numbered from (row) 1: (column) 1 to (row) 5: (column) 4. The execution unit is responsible for carrying out all computations. However, the execution unit can only operate on data that has been loaded into one of the four registers (A, B, C, or D). Let's say we want to find the product of two numbers - one stored in location 1:3 and another stored in location 4:2 and store back the result to 1:3.

CISC Approach

CISC design would try to finish the task in the minimum possible instructions by implementing hardware which could understand and execute series of operations. Thus the processor would come with a specific instruction ‘MUL’ in its instruction set. ‘MUL’ will load the two values from the memory into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate location. So, the entire task of multiplying two numbers can be completed with one instruction:

MUL 1:3, 4:2

MUL is referred to as a "complex instruction" as it operates directly on the computer's memory banks and does not require the programmer to explicitly call any loading or storing functions.

RISC Approach

RISC processors use simple instructions that can be executed within a clock cycle. Thus, ‘MUL’ instruction will be divided into three instructions.

(i) "LOAD," which moves data from the memory bank to a register,

(ii) "PROD," which finds the product of two operands located within the registers, and

(iii) "STORE," which moves data from a register to the memory banks.

In order to perform the task, a programmer would need to code four lines of assembly:

LOAD A, 1:3

LOAD B, 4:2

PROD A, B

STORE 1:3, A

Well, that's all on the Classification of Instruction Set Architectures. We shall discuss Micro Architecture in the next article.

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